Accumulator bounds: SYCL and Metal¶

Appendix of integer accumulator bounds: every integer accumulator, size product and offset of the SYCL and Metal feature twins and their runtimes, read on master 571565a47 (before the fixes the main page lists). Rows marked OVERFLOW or DEPENDS name their state row on the main page.

• Source: master 571565a47. Read only: nothing edited, built or run on a device. Commands were grep, sed, cat and python3 bound arithmetic; the scale-0 ADM row replay scripts/dev/adm_cm_row_bound.py was re-run.
• Scope (166 files): every file under core/src/feature/sycl/, core/src/sycl/, core/src/feature/metal/ and core/src/metal/, plus the shared core/src/feature/*.h helpers those twins include for integer math (adm_gain_limit.h, adm_angle_flag.h, adm_cm_accumulator.h, float_psnr_rows.h, ordered_sum.h, float_moment_sum*.h, ff_math.h), where the CUDA and HIP appendix is cited instead of re-derived.
• Envelope: 16K = 15360 x 8640, N = 132,710,400 (< \(2^{27}\)); 8K DCI 8192 x 4320; 1080p N = 2,073,600. Cap: W, H <= 32768, N <= \(2^{30}\). Samples up to 16 bit (65535; \(65535^{2}\) = 4,294,836,225), 4:4:4, worst-case content. "Out-of-range codewords" means uint16 samples above \(2^{\mathrm{bpc}} - 1\) at bpc 9-15, which no libvmaf entry point rejects (prior audit, common root of rows 8-10).
• Paths: feature rows name the file under core/src/feature/sycl/ or core/src/feature/metal/ by its basename (the summary below writes them as sycl/<file> / metal/<file>); runtime rows carry sycl/ or metal/ relative to core/src/; shared headers are under core/src/feature/. Every row is labelled SYCL or Metal.

Verdict totals (340 rows)¶

Every row that is not SAFE¶

OVERFLOW@16K¶

1. **SYCL integer ADM scale-0 contrast-masking row total, int64_t** (sycl/integer_adm_sycl.cpp:1127-1141 per-item cm[b] += for DLM and AIM, :1146-1158 sub-group reduce_over_group, :1184-1189 row_total += lmem, :1164-1174 fold).
2. Term per column (adm_dev_cm_cube, :1085-1098, shifts from adm_cm_shifts, :1264-1276): x_sq = (x^2 + 2^28) >> 29, then (x_sq * x + rnd) >> (ceil(log2 Wb) - 4) for h/v (>> 30, - 3 for d); x is the scale-0 excess |rfactor * v| - thr * 2^shift, the CPU's formula exactly.
3. Worst case: thr = 0 (ref == dis for DLM; a flat reference for AIM), x = |band| * weight. scripts/dev/adm_cm_row_bound.py (re-run) gives the exact row maximum over column sign patterns: 1.0207 * INT64_MAX = 9.414e18 at W = 64 (cols 28), 0.973 at W = 128, 0.855 at 15360, 0.912 at 8K DCI / 16384 / 32768, at the default weights 36,453 (h/v) and 49,417 (d).
4. W = 63-64 is inside the envelope (adm_frame_size_check admits W >= 17), so the signed sub-group / work-group int64 sums wrap at default options. Non-default CSF weights (h/v >= 38,406 or d >= 60,965 at 16K, below the budget 46,603 / 65,536) wrap at every size.
5. Known item 2, confirmed for SYCL. Same defect as the CPU integer_adm_kernels.h:1017-1019, 1079-1099 and CUDA/HIP prior row 2. The frame accumulator (fetch_add of rows >> ceil(log2 Hb)) cannot wrap (< 0.875 * \(2^{63}\) for any int64 row), so the visible effect is a negative or wrong band numerator, then NaN or a wrong score.
6. **Metal float VIF moment-plane index, uint** (metal/float_vif.metal:117-122 store, :160-163 read; plane = scale_w[0] * scale_h[0] from float_vif_metal.mm:563-565, 586-588).
7. moments[k * plane + at], k = 0..4: the largest index is 5 * plane - 1, which wraps once plane >= 858,993,460.
8. vif_prescale (option range 0.1 - 4.0, float_vif_metal.mm:190-198, same as the CPU) scales the scale-0 plane: at 16K, prescale > 2.545 wraps (prescale 4: plane 2,123,366,400, largest index 1.06e10). At the default prescale 1.0 it wraps above N = 858,993,459 (e.g. 29,310 x 29,310), inside the cap envelope.
9. The k >= 2 moment planes then alias the start of the buffer. The host sizes the buffer in size_t (float_vif_metal.mm:421-423, 42 GB at 16K prescale 4), so on most devices allocation fails first; where maxBufferLength admits it, the wrap is silent. SYCL float_vif indexes in size_t (SAFE).

OVERFLOW@CAP-ONLY¶

1. **SYCL PSNR-HVS prefix scan stops at 32,768 chunks** (sycl/integer_psnr_hvs_sycl.cpp:787-795, compaction :822-833).
2. limit = num_chunks < 32768u ? num_chunks : 32768u; num_chunks = ceil(total_blocks / 256); 16K 4:4:4 has 8,122,188 blocks = 31,728 chunks (3.2 % margin). Above 8,388,608 blocks (16384 x 8640 4:4:4: 8,662,680; luma-only above ~20.3K x 20.3K; cap 4:4:4: 256,779 chunks) chunk_offsets[c >= 32768] are never written, d_scratch (malloc_device, :956-957) is not cleared, and the compaction writes packed_terms + chunk_offsets[chunk] + intra from stale offsets: out-of-bounds device writes, short total_terms, wrong or NaN scores.
3. Known item 5, confirmed for SYCL (identical to HIP prior row 3). The uint32_t running sum is safe (<= 4,207,058,112 at the cap). Metal has no compaction (terms at (ulong)slot * 64), so the item is refuted there.
4. **SYCL SpEED covariance divisor rounded to fp32** (sycl/speed_sycl_pipeline.cpp:808-809): static_cast<float>(a.sub_w * a.sub_h).
5. Not a wrap (uint32 product <= 67,010,596). The count is exact at 16K for every prescale (largest 3836 * 2156 = 8,270,416 < \(2^{24}\)). Above 16K with prescale > ~2 it can be inexact (W = H = 32740 at prescale 4: \(8181^{2}\) = 66,928,761, odd), while the CPU speed.c:847 divides by the exact double. The mean divisor (:687) rounds the same way the CPU compute_mean does (SAFE).
6. Known item 4, confirmed (already being fixed). Metal has no SpEED twin.
7. **Metal integer SSIM moment-plane index, uint** (metal/integer_ssim.metal:74-80, :97, :115, :131-138): hbuf[k * plane + index], plane = W * H, k = 0..4 (five int64 planes). Largest index 5N - 1 wraps once N >= 858,993,460 (e.g. 32768 x 26,215): 16K is 0.15 * \(2^{32}\), the cap 1.25 * \(2^{32}\). The y2 plane then aliases the mux plane. Host buffer is size_t, 34 GB there (integer_ssim_metal.mm:223); init checks only W, H >= 1. SYCL integer SSIM indexes in size_t (SAFE).
8. **Metal float_ms_ssim moment-plane index, uint** (metal/float_ms_ssim.metal:115-126, :142-148): same shape, plane = (W - 10) * H at scale 0, which MS-SSIM always runs at full resolution. Wraps at default options once (W - 10) * H >= 858,993,460 (e.g. 32768 x 26,223); 16K: 663,119,999 (SAFE).
9. **Metal float_ssim moment-plane index, uint** (metal/float_ssim.metal:80-86, :94-100): same as row 6, reachable only with the scale=1 option pinned (the auto scale is >= 2 for min(W, H) >= 384 and init refuses, float_ssim_metal.mm:203-209).
10. **Metal float VIF host plane product, unsigned** (metal/float_vif_metal.mm:563-565, 586-588): scale_w * scale_h passed as uint32_t plane. Fits at 16K for every prescale (2,123,366,400 at prescale 4); above 16K with prescale >= 2.0 it wraps (\(65536^{2}\) = \(2^{32}\)).
11. **Metal float VIF term index, uint** (metal/metal_float_vif_math.h:171-175, used at float_vif.metal:169, 199): (x * height + y) * 2, largest 2 * plane - 1. 16K prescale 4: 4,246,732,799 (1.1 % below \(2^{32}\), SAFE); wraps for plane >= \(2^{31}\) (prescale > 1.414 at the cap).

DEPENDS¶

1. **SYCL integer PSNR clip apsnr_sse[p] += sse, uint64_t** (sycl/integer_psnr_sycl.cpp:550) and **11. Metal** (metal/integer_psnr_metal.mm:386). One frame adds up to N * \(65535^{2}\). Frames to wrap at 16-bit max-diff: 1080p 2,072; 8K DCI 122; 16K 33; cap 5 (\(2^{64}\) / (N * 4,294,836,225) = 2071.3, 121.4, 32.4, 4.0). 12 bit: 530,502 / 31,085 / 8,290 / 1,025. 10 bit: 8.50M / 498,076 / 132,821 / 16,417. 8 bit: 136.8M / 8.0M / 2.14M / 264,205. Silent wrap, APSNR too high. Known item 1, confirmed for both; same type as the CPU integer_psnr.c:211, 249 and CUDA/HIP prior rows 6-7.
2. **SYCL integer PSNR per-item SSE, uint32_t** (sycl/integer_psnr_sycl.cpp:168-172, instantiated for bpc <= 12 at :198). 16 squares per work-item: in range <= 16 * \(4095^{2}\) = 268,304,400; with out-of-range codewords at bpc 9-12 two squares of \(65535^{2}\) already exceed \(2^{32}\). The CPU sums 16-bit rows in uint64 (integer_psnr.c:129-135), so SYCL then differs from the CPU. Not frame-size dependent.
3. **SYCL motion vertical sum, int32_t** (sycl/integer_motion_pipeline_sycl.cpp:99-103, chosen for bpc <= 15 at :46, 224-225). In range (bpc 15) the sum is at most 65536 * 32767 + 16384 = 2,147,434,496, 49,151 below INT32_MAX. With out-of-range codewords at bpc 9-15 it reaches 65536 * 65535 = 4,294,901,760 (the first two products alone 2.57e9): signed overflow (UB). The CPU (integer_motion.c:226-231) and CUDA's 16 bpc kernel use int64; Metal uses long (SAFE).
4. **SYCL float_ssim decimation fixed point, int64_t** (sycl/integer_ssim_sycl.cpp:269-273, :290-302, sample scale :625-641). Each product (raw * sample_scale) * (1 / scale^2) is converted to units of \(2^{-52}\) and the scale x scale window is summed. In range the window mean is <= 255.996, so the sum is < \(2^{60}\). With out-of-range codewords the mean reaches raw / 4 = 16,383.75 at bpc 10 or raw / 16 = 4,095.94 at bpc 12, i.e. \(2^{66}\) or \(2^{64}\) in those units: the sum overflows once the window mean reaches 2048 (raw >= 8192 at bpc 10, raw >= 32768 at bpc 12), and at bpc 10, scale 2 a single product overflows the float-to-int64 conversion. The CPU forms the sum in double. The same exposure exists in the CUDA (cuda/integer_ssim/ssim_score.cu:317) and HIP (hip/float_ssim/ssim_decimate.h:89) twins, which the prior G4a rows marked SAFE assuming in-range samples (aside B1).
5. **SYCL integer VIF horizontal mean sum, uint32_t** (store sycl/integer_vif_sycl.cpp:490-491 and fused :1201-1204, both without the (uint16_t) the CPU integer_vif.c:450-451 applies; sums :777-778, 793-794, 828-829, fused :1239-1240, 1255-1256). In range tmp <= 65535 and the 17-tap sum <= 4,294,901,760; for bpc 9-15 with out-of-range codewords tmp reaches 8,388,480 (bpc 9) and the sum 5.5e11, which wraps. Known item 7, confirmed for SYCL (same as HIP prior row 9).
6. **SYCL integer VIF rd (next-scale) sum, uint32_t** (store :504-505, fused :1210-1214, sums :784-785, 802-803, 837-838, fused :1246-1247, 1264-1265, then dev_downsample_rd :748-753). Same cause for ref_convol (CPU integer_vif.c:205-206 truncates); the later & 0xFFFF cannot undo a wrapped 32-bit sum. Same as HIP prior row 10.
7. **Metal integer VIF decimate_16 rd sum, uint** (metal/integer_vif.metal:665-677, filt_scale == 1): v_ref_r = (v_ref + round) >> bpc is not narrowed to ushort, so acc_ref += cj * v_ref_r (9 taps) reaches 5.5e11 at bpc 9 with out-of-range codewords and wraps. The Metal mean path does truncate ((ushort), :343, 486), so known item 7 holds for Metal only on this rd path.
8. **SYCL integer ADM scale-0 flt narrowed to int16** (sycl/integer_adm_sycl.cpp:856-861, adm_i16((4369 * |csf| + 2048) >> 12)) and **19. Metal** (metal/integer_adm.metal:672-677, stored with iadm_write16). Wraps negative once |csf| >= 30,720, i.e. an h/v CSF weight >= 43,900 (budget 46,603; default 36,453 gives flt <= 27,212). Option-dependent, bit-identical with the CPU (integer_adm_kernels.h:488-489) and CUDA/HIP prior row 12. The Metal AIM pass (:1083-1100) forms the same flt inline in int without narrowing, so with such weights its AIM threshold differs from the CPU's.
9. **SYCL integer ADM scale-0 x_sq narrowed to int32** (sycl/integer_adm_sycl.cpp:1094-1095). Fits while thr >= 0 (h/v x <= 1.0686e9 at the budget: x_sq <= 2.127e9; d: 2.103e9). A negative thr from row 18 lets the excess reach the INT32_MAX clamp, x_sq = \(2^{33}\), which narrows modulo \(2^{32}\). As CUDA/HIP prior row 13.
10. **Metal integer ADM scale-0 cube in long** (metal/integer_adm.metal:759-765, called at :883-884, 1107-1108). Metal keeps x_sq in 64 bits (the CPU narrows to int32); with thr >= 0 x_sq * x <= 3.16e18, but with x = INT32_MAX (row 19's negative thr) x_sq * x = 2^33 * 2^31 = 2^64 overflows long.
11. **Metal integer ADM scale-0 contrast-masking row, ulong** (metal/integer_adm.metal:836-896, 1066-1115; carry-correct atomic_uint pair :728-750). The row that wraps int64 elsewhere (row 1: 9.414e18 at W = 64) is 0.51 * \(2^{64}\) here, so at default weights Metal does not wrap and returns the arithmetically correct value where the CPU, SYCL, CUDA and HIP overflow (a cross-backend mismatch, not a Metal defect). The term grows with \(\mathrm{weight}^{3}\): an h/v weight >= ~45,600 (budget 46,603) wraps the ulong row too. Known item 2, refuted for Metal at default options.
12. **Metal integer ADM host frame sum, int64_t** (metal/integer_adm_metal_host.c:305-315, t.cm[band] += (int64_t)iadm_slot(...), same for AIM). Rows are folded by >> ceil(log2 Hb) and rows / \(2^{s}\) <= 0.875, so at default weights the sum is <= 0.875 * 9.414e18 = 0.89 * INT64_MAX (SAFE); with an h/v weight >= ~37,850 (W = 63-64) the signed host sum can wrap. The SYCL/CUDA/HIP frame accumulators avoid this only because their rows have already wrapped.

Known items 1-8¶

Asides (not a verdict change; worth a ticket)¶

• B1 (CUDA/HIP, outside this scope): float_ssim decimation with out-of-range codewords. Row 14's int64 fixed-point window sum is shared by cuda/integer_ssim/ssim_score.cu:317 (__float2ll_rz saturates each product, the int64 sum then wraps) and hip/float_ssim/ssim_decimate.h:89 ((int64_t) of an out-of-range float is UB). The prior G4a bound (<= 255.996 * 2^52 < 2^60) holds only for samples <= \(2^{\mathrm{bpc}} - 1\).
• B2 (common root). Rows 12-17 all need uint16 codewords above \(2^{\mathrm{bpc}} - 1\). Only CAMBI validates samples against bpc (SYCL launch_validate, integer_cambi_sycl.cpp:355-375, as cambi.c does). A single check at picture import would retire every out-of-range DEPENDS row in all backends.
• B3 (Metal 32-bit indices, zero headroom). float_moment.metal:120-121, 154-155 and integer_motion_v2.metal:132, 224 form byte offsets in int: 32767 * 65536 = 2,147,418,112 at the cap, 65,535 below INT32_MAX. Safe only because the host always packs rows (row_bytes = W * bpp); any padded stride at H = 32768 would wrap. float_ms_ssim_metal.mm:371 (window_offset, unsigned) reaches 4,282,811,768 = 0.997 * \(2^{32}\) at the cap with 4:4:4 and enable_chroma.
• B4 (SYCL id queries). icpx compiles with -fsycl-id-queries-fit-in-int by default (Intel DPC++ developer guide), so global ids and linear ids must fit int. Every SYCL range in scope stays below INT_MAX at 16K, including float_vif's range<1>(pixels) at prescale 4 (2,123,366,400, 1.1 % below). Above 16K that range can exceed INT_MAX; the DPC++ runtime then rejects the launch rather than wrapping.
• B5 (Metal buffer sizes). The CAP-ONLY Metal rows (5-9) need buffers of 21-42 GB; on a device whose maxBufferLength is smaller the allocation fails cleanly (-ENOMEM) before the wrap. The defect is the 32-bit index, not the allocation.
• B6 (Metal vs CPU ADM). Row 22: at W = 63-64 and default options Metal returns a correct scale-0 ADM numerator where every other backend (CPU included) wraps int64. Fixing row 1 in the CPU/SYCL/CUDA/HIP sum (e.g. an unsigned 64-bit row as Metal does, or a 128-bit row) would restore cross-backend agreement.

Verification log¶

• Row 1: read integer_adm_sycl.cpp:1000-1276 (cube, shifts, row reductions, fold) and :405-452, :719-975; re-ran scripts/dev/adm_cm_row_bound.py (output in the table above); confirmed adm_frame_size_check admits W >= 17.
• Row 2 and rows 8-9: read float_vif.metal in full, metal_float_vif_math.h:68-176, float_vif_metal.mm:350-440, 555-600; option range at float_vif_metal.mm:190-198, default vif_options.h:43 (1.0).
• Row 3: read integer_psnr_hvs_sycl.cpp:676-860, 940-1220.
• Row 4: read speed_sycl_pipeline.cpp:640-850.
• Rows 5-7: read integer_ssim.metal, float_ssim.metal, float_ms_ssim.metal in full and the host allocation / geometry code of each .mm; thresholds from python (5N - 1 vs \(2^{32}\)).
• Rows 10-12: read integer_psnr_sycl.cpp:140-300, 540-560, integer_psnr_metal.mm:300-430, CPU integer_psnr.c:119-250.
• Row 13: read integer_motion_pipeline_sycl.cpp in full and CPU integer_motion.c:164-257.
• Row 14: read integer_ssim_sycl.cpp:86-345, 540-680; cross-checked the CUDA and HIP decimation lines named in B1.
• Rows 15-17: read integer_vif_sycl.cpp:330-1320, integer_vif.metal in full, CPU integer_vif.c:195-215, 400-460.
• Rows 18-23: read integer_adm.metal:280-1209, metal_integer_adm_math.h, integer_adm_metal_host.c:290-320.

Runtime: SYCL (core/src/sycl/) and Metal (core/src/metal/)¶

No integer accumulators over pixels. Rows are size products, offsets and pitches.

SYCL shared headers (feature/sycl/sycl_*.h)¶

sycl_compat.h, sycl_ff_math.h, sycl_ciede_math.h, sycl_ssim_terms.h (beyond the soft-signed calls above) and sycl_float_adm_math.h / sycl_float_vif_math.h (float arithmetic; their integer parts are rows in the feature sections) hold no integer accumulator.

Metal shared headers (metal_soft_double.h, metal_soft_signed.h, metal_portable.h)¶

metal_soft_double.h and metal_soft_signed.h are line-for-line ports of the SYCL headers above (their own comments map every name); the same rows apply.

psnr (integer)¶

Per-pixel term: |ref - dis|^2, at most \(65535^{2}\) = 4,294,836,225 for any uint16 sample. In range (samples <= \(2^{\mathrm{bpc}} - 1\)) the term is at most \((2^{\mathrm{bpc}} - 1)^{2}\).

SYCL (feature/sycl/integer_psnr_sycl.cpp)¶

Metal (feature/metal/integer_psnr.metal, integer_psnr_metal.mm)¶

float_psnr¶

Term (CPU float_psnr.c): diff * diff in fp32, in units of 1 / \(\mathrm{scaler}^{2}\); at most fl32(\(65535^{2}\)) = 4,294,836,224 for any uint16 sample.

SYCL (feature/sycl/float_psnr_sycl.cpp; host tail feature/float_psnr_rows.h)¶

Metal (feature/metal/float_psnr.metal, metal_float_psnr_math.h, float_psnr_metal.mm)¶

float_moment¶

Terms: first moment <= 65535; second moment moment_float_square(v) = fl32(v*v) <= 4,294,836,224. The past-\(2^{53}\) ordered-sum machinery is the shared float_moment_sum.h (prior audit G3b, SAFE) or its Metal port.

SYCL (feature/sycl/integer_moment_sycl.cpp)¶

Metal (feature/metal/float_moment.metal, metal_float_moment_math.h, metal_float_moment_sum.h, float_moment_metal.mm)¶

ciede¶

Per-pixel float term, no integer accumulator; the frame sum is ciede_frame_sum() in double. Rows are index math.

motion, motion_v2 (integer SAD) and float_motion¶

Derivation (same as prior G3a): taps {3571, 16004, 26386, 16004, 3571}, sum \(2^{16}\). Vertical v = (sum f_k d_k + 2^(bpc-1)) >> bpc; |sum| <= 65536 * |d|max. In range |d| <= \(2^{\mathrm{bpc}} - 1\), so |sum| <= 65536 * (\(2^{\mathrm{bpc}} - 1\)); for any uint16 sample |d| <= 65535 and |sum| <= 4,294,901,760. Horizontal h = (sum f_k v_k + 2^15) >> 16; |h| <= 65535 in range, <= 8,388,480 for out-of-range bpc 9 input. Frame SAD in range <= N * 65535: 16K 8.70e12, cap 7.04e13. SAD accumulators are cleared every frame; no clip-level integer sum.

SYCL (integer_motion_pipeline_sycl.cpp, shared by integer_motion_sycl.cpp and integer_motion_v2_sycl.cpp)¶

Metal (integer_motion.metal, metal_integer_motion_math.h, integer_motion_metal.mm; integer_motion_v2.metal, integer_motion_v2_metal.mm)¶

float_motion: SYCL (float_motion_sycl.cpp) and Metal (float_motion.metal, metal_float_motion_math.h, float_motion_metal.mm)¶

fp32 blur and fp32 row sums (never converted to an integer); rows are index math and the small-frame mirror (known item 8).

ssim (integer), float_ssim, float_ms_ssim¶

Term maxima for integer SSIM (prior G4a): 9 taps {2,9,28,55,68,55,28,9,2}, sum 256. Horizontal mux/muy <= 256 * 65535 = 16,776,960; x2/xy/y2 <= 256 * \(65535^{2}\) = 1.10e12. Vertical mux <= 65536 * 65535 = 4,294,901,760 = \(2^{32}\) - \(2^{16}\); x2 <= 65536 * \(65535^{2}\) = 2.81e14; w <= 65536. These hold for any uint16 sample. Products: \(\mathrm{mux}^{2}\) <= (\(2^{32}\) - \(2^{16}\))^2 = \(2^{64}\) - \(2^{49}\) + \(2^{32}\); x2 * w <= \(2^{32}\) * \(65535^{2}\) = the same value. Both are below \(2^{64}\) by \(2^{49}\) - \(2^{32}\).

SYCL integer SSIM (integer_ssim_sycl.cpp second half, sycl_integer_ssim_math.h)¶

SYCL float_ssim (integer_ssim_sycl.cpp first half) and float_ms_ssim (integer_ms_ssim_sycl.cpp)¶

Metal integer SSIM (integer_ssim.metal, metal_integer_ssim_math.h, integer_ssim_metal.mm)¶

Metal float_ssim (float_ssim.metal, metal_ssim_terms.h, float_ssim_metal.mm) and float_ms_ssim (float_ms_ssim.metal, metal_ms_ssim_math.h, float_ms_ssim_metal.mm, float_ms_ssim_option_semantics.h)¶

Both twins take float planes from picture_copy() on the host (no fixed-point decimation), so the SYCL decimation row above has no Metal counterpart.

ssimulacra2¶

The six per-pixel sums are fp64 values formed in integers (SYCL) or summed in double on the host (Metal). The SYCL chunk increments go through the shared ordered_sum.h composition, capped at \(2^{54}\) (prior G4b, N-independent). Chunk = 512 pixels (SYCL).

vif (integer)¶

Basis (prior G2): every filter row sums to 65536; widths {17, 9, 5, 3}; largest tap 43,728 (scale 3). Scale-0 vertical shift is bpc, square shift 2(bpc - 8); scales 1-3 shift 16. The CPU (integer_vif.c:205-206, 450-451) truncates the vertical mu1, mu2 and ref_convol/dis_convol to uint16_t before the horizontal pass; for in-range samples the truncation is a no-op. For bpc 9-15 with codewords above \(2^{\mathrm{bpc}} - 1\) the untruncated vertical value reaches (65536 * 65535 + \(2^{\mathrm{bpc}-1}\)) >> bpc, i.e. 8,388,480 at bpc 9 (prior rows 9-10). Accumulators are per frame and per scale (memset each frame).

SYCL (integer_vif_sycl.cpp, sycl_integer_vif_math.h)¶

Metal (integer_vif.metal, metal_integer_vif_math.h, metal_integer_vif_gain.h, integer_vif_metal.mm)¶

float_vif¶

Float arithmetic; integer content is index math, plus the soft-fp64 helpers of sycl_float_vif_math.h / metal_float_vif_math.h. The vif_prescale option (0.1 - 4.0, float_vif_metal.mm:190-198, float_vif.c) scales the scale-0 plane: at 16K and prescale 4 the plane is 61440 x 34560 = 2,123,366,400 samples.

adm (integer)¶

Constants (integer ADM group): DWT taps lo {15826, 27411, 7345, -4240}, hi {-4240, -7345, 27411, -15826}, abs sum 54822. Band maxima: scale 0 <= 22,930; scale 1 <= 1,491,390,732 (band_a), h/v/d <= 1,448,979,042; scales 2-3 <= 751,510,749. CSF weight budgets: scale-0 h/v < 46,603.4, d < 65,536; defaults 36,453 (h/v), 49,417 (d). Region: cols = Wb - 2 * int(0.1 * Wb - 0.5). The scale-0 contrast-masking row term is ((x^2 + 2^28) >> 29) * x >> (ceil(log2 Wb) - 4) (h/v; d: shifts 30 and -3); its exact row maximum over column sign patterns is the scripts/dev/adm_cm_row_bound.py replay, re-run for this audit: 0.855 * INT64_MAX at W = 15360, 0.912 at 8K DCI / 16384 / 32768, 0.973 at W = 128 and **1.0207 at W = 64 (9.414e18)**, all at default weights.

SYCL (integer_adm_sycl.cpp; shared adm_gain_limit.h, adm_angle_flag.h, adm_cm_accumulator.h)¶

Metal (integer_adm.metal, metal_integer_adm_math.h, metal_integer_adm_uniforms.h, integer_adm_metal_host.c, integer_adm_metal.mm)¶

Metal has no 64-bit atomics: each (band, row) threadgroup reduces through a pair of 32-bit atomics with an explicit carry and stores a 64-bit value as two uint words; the host adds the words.

adm (float)¶

Float arithmetic with soft-fp64 replays; integer content is index math.

cambi¶

Bounds (prior G5): vmaf_cambi_check_window_fits_lut() limits the window to 65 x 65 (4,225 pixels) at any resolution (SYCL integer_cambi_sycl.cpp:1719-1734, Metal integer_cambi_metal.mm:512-516); levels <= 1056; c-value < 9506.25, fixed point (x \(2^{24}\)) < \(2^{37.22}\) = F. Out-of-range samples are flagged (launch_validate, SYCL :355-375) as on the CPU. Per-frame only.

psnr_hvs¶

Bounds (prior G5): every implementation rejects bpc > 12 (SYCL integer_psnr_hvs_sycl.cpp:863, Metal integer_psnr_hvs_metal.mm:196), so samples are <= 4095. DCT intermediates <= 32,795, lifting products <= 379,769,216 (\(2^{28.5}\)), \(\mathrm{AC}^{2}\) <= \(2^{28.0}\). Blocks: step 7, 16K 4:4:4 total 8,122,188 (2,707,396 per plane), cap 4:4:4 65,735,283.

speed_chroma / speed_temporal (SYCL only; Metal has no SpEED twin)¶

Geometry (prior G6): the scaled plane is lround(src * speed_prescale), prescale in [0.1, 4.0]; at 16K and prescale 4 it is 61440 x 34560; at the cap and prescale 4, 131072 x 131072. sub_w * sub_h at 16K p4 = 3836 * 2156 = 8,270,416; at cap p4 = \(8186^{2}\) = 67,010,596. Every pixel sum is fp32 or an fp32 pair; integers are sizes and indices.

Coverage¶

Every file under the four scope directories, with the number of table rows that cite it in the file:line column (a row may cite several files). "none" means the file was read and holds no integer accumulator, size product or index math beyond what the note says.