Accumulator bounds: CPU and SIMD¶

Appendix of integer accumulator bounds: every integer accumulator, size product and offset of the CPU feature extractors, their x86 (AVX2, AVX-512) and arm64 (NEON, SVE2) SIMD paths and the core/src/ runtime, read on master 571565a47 (before the fixes the main page lists). Rows marked OVERFLOW or DEPENDS name their state row on the main page.

• Source: master 571565a47.
• Mode: read only. Nothing was edited, built or run. Commands: grep, sed, cat, and one python3 call that recomputed the bounds quoted below.
• Paths: relative to core/src/feature/ unless they start with core/src/.
• Envelope: 16K W ≤ 15360, H ≤ 8640, N = 132,710,400; 8K DCI 8192x4320; cap W, H ≤ 32768 (VMAF_PIC_DIM_MAX, core/src/picture.c:46), N ≤ \(2^{30}\); samples up to 16 bit; 4:4:4; worst-case content.
• Group of a row: x86/... = x86 SIMD, arm64/... = arm64 SIMD (NEON and SVE2), everything else = CPU scalar (feature code plus the runtime size products in core/src/).
• Already established (cited, not re-derived): integer_psnr line SSE; psnr apsnr clip sum (DEPENDS; fixed since, T-PSNR-APSNR-CLIP-SSE-UINT64-WRAP-2026-10-05); integer_motion / motion_v2 row_sad; integer_vif frame accumulators; integer ADM csf_den (shift adapts); integer ADM scale-0 CM row int64 (OVERFLOW at W = 31–32 / 63–64, fix to uint64 in flight); cambi histograms uint16 (window ≤ 65, counts ≤ 4225); integer_ssim window moments int64 (≤ \(2^{48}\)). The SIMD twins of each were checked here.
• "Out-of-range input": libvmaf does not range-check samples (cambi is the exception, cambi.c:990-1029), so a 10- or 12-bit picture can carry 16-bit values. Rows where that makes a CPU integer accumulator or narrowing wrap are DEPENDS (out-of-range input), because the GPU twins can differ there.

Summary¶

Of the 27 DEPENDS rows, 1 depends on clip length (apsnr), 20 on out-of-range input, 6 on the ADM CSF weight option.

New defects (not on the established list):

1. **x86 sad_avx512 (test-only sub-kernel): int16 lane wrap on 16-bit samples** (OVERFLOW@16K, independent of size).
2. **float_vif / SpEED with vif_prescale or speed_prescale above √2 at 32768²: int pixel index overflows** (OVERFLOW@CAP-ONLY, non-default option; SAFE at 16K for every prescale up to the option maximum of 4.0).
3. **AVX2 / AVX-512 integer motion x_conv: int32 lane products wrap on out-of-range samples where the scalar's int64 does not** (DEPENDS: out-of-range input; the twins then differ from the scalar before the shared row_sad wrap).
4. **AVX2, AVX-512 and NEON integer VIF 16-bit vertical / subsample passes keep the 32-bit filtered mean where the scalar narrows it to uint16** (DEPENDS: out-of-range input; then 32-bit packed-pair carries / 16-bit-half multiplies give garbage).
5. **AVX2 ADM scale-0 CSF flt saturates (packs_epi32) where the scalar and AVX-512 wrap the int16** (DEPENDS: CSF weight option, h/v weight ≥ 43,900).
6. **psnr_hvs (scalar, AVX2, NEON) DCT on out-of-range samples overflows int** (DEPENDS: out-of-range input; bpc ≤ 12 is guarded but the sample values are not).
7. **integer_vif scalar and ADM 16-bit DWT narrowings on out-of-range samples** (DEPENDS: out-of-range input).

Every row that is not SAFE¶

OVERFLOW@16K¶

1. **CPU integer_adm_kernels.h:1017-1019 (inner[]), :1079-1099 (adm_cm_rows), fold :892 + adm_cm_accumulator.h:30-34: scale-0 contrast-masking row total, int64_t.** Established (fixed since: summed in uint64_t, T-ADM-CM-SCALE0-ROW-INT64-OVERFLOW-2026-10-05). Term ((x² + 2^28) >> 29)·x >> (ceil(log2 Wb) − 4) (h/v; d uses 30 / −3); worst case thr = 0 (ref == dis or flat ref), x = |band|·weight. Row max at default weights: 0.855·INT64_MAX at W = 15360, 0.912 at 8K DCI and at the cap; **overflows at W = 31–32 and 63–64** (1.021·INT64_MAX at 16-bit, W = 63–64), which lies inside the envelope. Non-default CSF weights overflow at every size (G1, audit-cuda-hip.md).
2. **x86 x86/adm_avx2.c:1274-1292 (cm_accum_avx2), :1365-1385 (cm_row_avx2): same row, biased uint64 lanes.** Each term is added as (a + 2^63) >>> n; the lanes wrap mod \(2^{64}\) by design and the row is hsum − lanes·(2^63 >> n) mod \(2^{64}\), read back as int64 (cm_as_int64). That equals the true row sum exactly when the true sum fits int64, so the AVX2 row inherits row 1 bit for bit (same W = 31–32 / 63–64 overflow; SAFE at 16K and cap at default weights). The rows of W = 63–64 take this vector path (cols ≈ 26 ≥ 6).
3. **x86 x86/adm_avx512.c:1310-1327 (cm_accum_avx512), :1394-1410 (cm_row_avx512): same row, int64 lanes with native srai, hsum_epi64.** Every lane holds a subset of the row's non-negative terms, so no lane wraps before the row does; the final sum inherits row 1 (cols ≈ 26 ≥ 14 at W = 63–64, so the vector path runs).
4. **x86 x86/motion_avx512.c:374-375 sad_avx512(): _mm512_sub_epi16(va, vb) then _mm512_abs_epi16 on uint16 samples.** The difference is formed in signed int16 lanes. For 16-bit content with |a − b| > 32767 it wraps: a = 65535, b = 0 gives −1, |·| = 1 instead of 65535; a = 40000, b = 0 gives 25536. The scalar tail (:384-386) uses int and is right, so the vector and tail columns disagree. Independent of frame size; samples ≤ 32767 (bpc ≤ 15 in range) are exact. Reached only from core/test/test_motion_avx512_parity.c (the header says "sub-kernel functions used by unit tests"); no production caller. Fix: _mm512_max_epu16(a,b) − _mm512_min_epu16(a,b) (or widen first). The lane sum (:376-382, ≤ 2048·65535 per lane, (uint32_t) reduce ≤ 32768·65535 < \(2^{32}\)) is SAFE.

OVERFLOW@CAP-ONLY¶

1. **CPU vif_tools.c:649 (bicubic), :733 (lanczos4), :840 (nearest, the default vif_prescale_method / speed_prescale_method): dst[y * dst_stride + x], int.** Called from float_vif.c:375-381 with dst_stride = scaled_float_stride / 4 and from SpEED (speed.c:1211-1213, speed_internal.c:137) with the alloc-width stride. With prescale p the output plane is (W·p)×(H·p). 16K, p = 4.0 (option max, float_vif.c:127, speed.c:1522): max index 34,559·61,440 + 61,439 = 2,123,366,399 < INT32_MAX (1.1 % margin): SAFE. Cap: (32768·p)² ≥ \(2^{31}\) once p ≥ √2 ≈ 1.4142; at p = 4 the index reaches \(2^{34}\). Signed overflow UB, out-of-bounds writes. Default p = 1.0 (vif_options.h:43, speed.c:1489,1706) only copies (memcpy). The bilinear path (:767-769) uses size_t and is safe. Memory for such a plane is ≥ 8.6 GB per float buffer, so this is reachable only on very large hosts, but nothing rejects it (vif.c:86-94 bounds only the row width).
2. **CPU vif_tools.c:193 (vif_dec2_s), :206 (vif_dec16_s), :221 (vif_sum_s), :328-331 (vif_statistic_s), :378, :397, :416-417 (vertical filter passes): i * px_stride + j in int.** float_vif runs compute_vif() (vif.c:241-262) on the prescaled plane; SpEED runs vif_filter1d_s, vif_dec16_s and vif_filter1d_dec16_s (speed.c:1238-1250) on it. Same bound as row 5: SAFE at 16K for p ≤ 4 (≤ 2,123,366,399), overflows at the cap for p > √2.
3. **CPU speed.c:1189-1214 (speed_prescale_frame) and speed_internal.c:131-139: SpEED's resample and filter call sites.** They hand (int) widths and strides to the vif_tools.c functions of rows 5 and 6; listed separately because they are the SpEED entry (speed_chroma, speed_temporal). Same verdict and threshold (speed_prescale > √2 at 32768², non-bilinear method, which includes the default "nearest").

DEPENDS¶

Clip-level (frame count):

1. **CPU integer_psnr.c:211, :249 s->apsnr.sse[p] += sse, uint64_t** (established; fixed since, T-PSNR-APSNR-CLIP-SSE-UINT64-WRAP-2026-10-05). Frames to overflow at 16-bit max difference (65535² = 4,294,836,225 per pixel): 1080p 2071.3 (wraps in frame 2072), 8K DCI 121.4 (frame 122), 16K 32.4 (frame 33), cap 4.0001 (frame 5). At 10-bit: 132,820 frames at 16K. At 8-bit: 2.14e6 frames at 16K. (n_pixels at :212,250 is SAFE: 1.4e11 frames at 16K.)

Out-of-range input (samples above \(2^{\mathrm{bpc}} - 1\)):

1. **CPU integer_motion.c:251 and 10. integer_motion_v2.c:255: 16-bit row_sad, uint32_t** (established). In range |val| ≤ 65,535 (bpc 16) → row ≤ 32768·65535 = 2,147,450,880 < \(2^{32}\). Out of range the y-conv output is (65536·65535) >> bpc: 4,194,240 at bpc 10 (wraps at W ≥ 1025), 1,048,560 at bpc 12 (W ≥ 4097). Wraps mod \(2^{32}\); the uint64 frame sum then under-counts.
2. **x86 x86/motion_avx2.c:91-92 (x_conv_abs8_avx2) and 12. x86/motion_avx512.c:83-84 (x_conv_abs16_avx512): _mm256/512_mullo_epi32(y, g) and the pair sums s04, s13 in int32 lanes.** In range |y| ≤ 65,535: s13 = 2·16004·65535 = 2,097,644,280 < INT32_MAX (2.3 % margin), y2·g2 = 1,729,206,510: SAFE. Out of range they wrap once |y| > 67,092 (s13) or 81,387 (y2·26386), i.e. for essentially every out-of-range bpc-10 sample, where the scalar forms the same sum in int64 (integer_motion.c:245-249). AVX2 / AVX-512 therefore diverge from the scalar before the row_sad wrap of rows 9–10.
3. **arm64 arm64/motion_v2_neon.c:145-149: sad_acc (uint32x4) and vaddvq_u32.** The NEON x-conv is int64 (vmull_s32, :96-106), so lanes see the scalar's values; per lane ≤ (W/4)·4,194,240 out of range, wrapping mod \(2^{32}\). The row total mod \(2^{32}\) equals the scalar's wrapped row_sad bit for bit. In range: lane ≤ 8192·65535, row ≤ 2,147,450,880: SAFE.
4. **CPU integer_vif.c:205 (subsample_rd_16, scale 0) and 15. integer_vif.c:450-452 (vif_vertical_line_16, scale 0): (uint16_t)((accum + 2^(b−1)) >> b) and (uint32_t)((accum_ref + r) >> 2(b−8)).** The uint32 / uint64 accumulators themselves never wrap (≤ 65536·65535 + 32768 = 4,294,934,528; ≤ 2.81e14). In range the narrowings are exact (mean ≤ 65,535; moment < \(2^{32}\)). Out of range at bpc 10 the mean reaches 4,194,240 and the moment 65536·65535²/16 = 1.76e13; both are truncated (mod \(2^{16}\), mod \(2^{32}\)).
5. **x86 x86/vif_avx2.c:659-672 (vif_vertical16_store_mean), used by the statistic and by vif_subsample16_vertical (:962-979).** Stores (acc + 2^(b−1)) >>> b as a full 32-bit value; the scalar narrows to uint16 (row 14–15). In range identical (≤ 65,535; the lane sum ≤ 4,294,934,528 < \(2^{32}\) even read unsigned). Out of range the stored mean exceeds 65,535, then vif_mean256 (:314-337) multiplies it in 32 bits (43,728·4,194,240 = 1.8e11 wraps) and adds packed 32-bit products with add_epi64, carrying into the neighbour dword; and the subsample horizontal pass (vif_multiply16, :618-624, :857-863) multiplies the two 16-bit halves of each 32-bit value separately. Garbage, and different from the scalar.
6. **x86 x86/vif_avx2.c:999-1030 (vif_subsample16_horizontal, _block)**: the 16-bit-half multiply of row 16 on the un-narrowed ref_convol. Listed with row 16's cause; SAFE in range (value ≤ 65,535, high half 0, sum ≤ 65536·65535 + 32768).
7. **x86 x86/vif_avx512.c:639-647 (vif_vertical_store_mean16)** and 19. **x86/vif_avx512.c:1191-1215, :1270-1311 (subsample16 store and horizontal)**: same as rows 16–17 for AVX-512.
8. **arm64 arm64/vif_neon.c:874-900 (vif_stat16_vertical8 → vif_store_round_shift_u32, :199-204)** and 21. **arm64/vif_neon.c:284-293, :373-390 (vif_subsample16_vertical16, vif_subsample_horizontal16)**: NEON stores the un-narrowed 32-bit mean too; out of range the u32 vmlaq_n_u32 sums of the next pass (65536·4.19e6) wrap mod \(2^{32}\). In range SAFE (≤ 4,294,934,528).
9. **CPU integer_adm_kernels.h:1318-1323: (int16_t)adm_dwt2_vpass16_tap4(...)** (the int64 tap itself, integer_adm.h:199-209, is SAFE). In range |result| ≤ 27,411. Out of range at bpc 10: (50582·65535 − 46342·512 + 512) >> 10 = 3,214,028 → int16 wrap. The AVX2 / AVX-512 16-bit DWT call this same scalar pass (x86/adm_avx2.c:729, x86/adm_avx512.c:771), so they inherit it; the CUDA / HIP twins narrow the same way (G1).
10. **CPU third_party/xiph/psnr_hvs.c:127-179 (od_bin_fdct8 lifting products (t·K + r) >> s, int)** and 24. **psnr_hvs.c:357, :362 (dct·dct, int)**. init rejects bpc > 12 (:440), which bounds the products at \(2^{28.5}\) and the AC squares at \(2^{28}\) (the affine bound of the CAMBI and PSNR-HVS group) — but only for in-range samples. A 10- or 12-bit picture with 16-bit values feeds the DCT 16x larger inputs: products reach \(2^{32.5}\), squares \(2^{36}\). Signed int overflow (UB).
11. **x86 x86/psnr_hvs_avx2.c:89-100 (od_mulrshift_avx2, _mm256_mullo_epi32)** and 26. **x86/psnr_hvs_avx2.c:461-466 (dct·dct, int)**: same as rows 23–24; the vector product wraps mod \(2^{32}\) where the scalar is UB.
12. **arm64 arm64/psnr_hvs_neon.c:105-112 (vmulq_s32)** and 28. **arm64/psnr_hvs_neon.c:500-505 (dct·dct)**: same.

CSF weight option (not frame size; shared with the GPU twins):

1. **CPU integer_adm_kernels.h:488-489: flt = (int16_t)((4369·|i16| + 2048) >> 12)** and **integer_adm_kernels.h:872: v_sq = (int32_t)((v² + 2^28) >> 29)** (one row each in the ADM section). Default weights: flt ≤ 27,212, v_sq ≤ 2.127e9: SAFE. An h/v weight in [43,900, 46,603) (adm_csf_scale in Barten modes, or viewing geometry) wraps flt negative; a negative threshold then lets the excess reach INT32_MAX and v_sq (\(2^{33}\)) wraps.
2. **x86 x86/adm_avx2.c:891-894 (csf_block_avx2): flt through _mm256_packs_epi32**, which **saturates** to 32,767 where the scalar wraps to e.g. 34,952 − 65,536 = −30,584. Under that option AVX2 diverges from the scalar and from AVX-512 (x86/adm_avx512.c:930-932 truncates with _mm512_cvtepi32_epi16, like the scalar; listed as its own DEPENDS row). The AVX2 and AVX-512 squared-excess narrowings (mul_epi32 reads the low 32 bits signed, x86/adm_avx2.c:1280-1283, x86/adm_avx512.c:1316-1319) match the scalar's (int32_t) and carry the same option dependence (one DEPENDS row each).

Not counted as defects but worth noting: - third_party/xiph/psnr_hvs.c:311-317 (and the AVX2 / NEON copies): (y + i)·_systride + (j + x)·2 + 1 in int reaches exactly 32767·65536 + 65535 = 2,147,483,647 = INT32_MAX at the cap (16-bit storage). SAFE with zero margin: a picture with a stride above 2·W (not produced by vmaf_picture_alloc) would wrap. - integer_adm_kernels.h:519-526 (called at :567, :1153): add_bef_shift_flt = (int32_t)(1u << 31) = INT32_MIN (ADR-0155 upstream rounding quirk). Implementation-defined conversion, not an accumulator; AVX2 / AVX-512 reproduce it.

PSNR (integer_psnr, psnr_score.h)¶

float_psnr, psnr.c¶

Motion (integer_motion, integer_motion_v2)¶

Filter taps {3571, 16004, 26386, 16004, 3571}, sum 65,536 (integer_motion.h:26). 8-bit y-conv output ≤ 65,280; 16-bit in range ≤ 65,535; out of range (bpc 10 / 12, samples 65535) ≤ 4,194,240 / 1,048,560.

float_motion, motion.c¶

Integer VIF¶

Filter tables sum to 65,536 per pass (integer_vif.h:39-44); the scale-3 centre tap 43,728 exceeds INT16_MAX, so every twin that multiplies it must use unsigned 16-bit multiplies (they do: mulhi_epu16, vmull_n_u16).

float VIF, vif_tools.c (also SpEED's filters and resampler)¶

Integer ADM¶

Band maxima, weight budgets and the region come from the integer ADM group of the CUDA and HIP appendix (adm_csf_fixed_point.h:88-127): scale-0 bands ≤ 22,930; scale 1 ≤ 1.449e9 (band_a ≤ 1.491e9); scale-0 weights ≤ 46,603 (h/v), 65,535 (d); scales 1–3 CSF output ≤ 1,518,500,221.

float ADM (adm.c, adm_tools.c, float_adm.c)¶

Integer SSIM¶

float SSIM, MS-SSIM, IQA¶

Moment (moment.c, float_moment.c, float_moment_sum.h, ordered_sum.h)¶

CAMBI¶

validate_image (cambi.c:990-1029) rejects samples above \(2^{\mathrm{bpc}} - 1\), so CAMBI has no out-of-range path. Internal samples are 10-bit.

PSNR-HVS (third_party/xiph/psnr_hvs.c, psnr_hvs_score.c)¶

SpEED (speed.c, speed_internal.c, speed_qa.c)¶

CIEDE, delta-E ITP¶

SSIMULACRA 2¶

Other CPU extractors and helpers¶

Runtime size products (core/src)¶

Coverage¶

Every in-scope file, with the number of table rows whose first cell names it (a row naming several files counts once for each; the non-SAFE narrative cites some of these rows again). "none" = read, no integer accumulator or size product. The GPU subtrees (cuda/, hip/, sycl/, metal/, rust/) are out of scope (other audits). x86/AGENTS.d/ and the AGENTS.md files are documentation.

CPU scalar, core/src/feature/ (top level, iqa/, common/, third_party/xiph/)¶

• adm.c: 2 rows
• adm_tools.c: 2 rows
• alias.c: none
• brisque.c: 1 row
• cambi.c: 11 rows
• ciede.c: 2 rows
• delta_e_itp.c: 1 row
• fastdvdnet_pre.c: 1 row
• feature_dists.c: 1 row
• feature_lpips.c: 1 row
• feature_mobilesal.c: 1 row
• float_adm.c: 1 row
• float_moment.c: 1 row
• float_motion.c: 2 rows
• float_ms_ssim.c: 2 rows
• float_psnr.c: 3 rows
• float_ssim.c: 2 rows
• float_vif.c: 2 rows
• integer_adm.c: 1 row
• integer_motion.c: 6 rows
• integer_motion_v2.c: 4 rows
• integer_psnr.c: 7 rows
• integer_ssim.c: 5 rows
• integer_vif.c: 14 rows
• moment.c: 1 row
• motion.c: 1 row
• ms_ssim.c: 2 rows
• ms_ssim_decimate.c: 1 row
• niqe.c: 1 row
• null.c: none
• offset.c: 1 row
• perceptual_weight.c: 1 row
• psnr.c: 1 row
• psnr_hvs_score.c: 1 row
• pu21.c: 1 row
• pu21_ssim.c: 1 row
• speed.c: 4 rows
• speed_internal.c: 2 rows
• speed_qa.c: 3 rows
• ssim.c: 2 rows
• ssimulacra2.c: 2 rows
• tad_rust.c: none (Rust FFI shim)
• transnet_v2.c: 2 rows
• vif.c: 3 rows
• vif_tools.c: 3 rows
• y_funque_plus.c: 1 row
• adm.h: none
• adm_angle_flag.h: 1 row
• adm_cm_accumulator.h: 3 rows
• adm_csf_fixed_point.h: 1 row
• adm_csf_tools.h: none
• adm_float_reference.h: none
• adm_gain_limit.h: 1 row
• adm_options.h: none
• adm_score.h: none
• adm_tools.h: none
• alias.h: none
• barten_csf_tools.h: none
• brisque_math.h: none
• brisque_model.h: none (double model constants; grep-checked)
• cambi.h: none (prototypes and the float reciprocal LUT; grep-checked)
• cambi_c_values_frame.h: none (size_t memsets, mask words)
• cambi_internal.h: none (prototypes; uint32_t *mask_dp)
• ciede_ff_math.h: 1 row
• ciede_frame_sum.h: 1 row
• compat_builtin.h: none
• delta_e_itp_math.h: 1 row
• feature_characteristics.h: none
• feature_collector.h: none
• feature_collector_internal.h: none
• feature_dimensions.h: none
• feature_extractor.h: none
• feature_name.h: none
• ff_math.h: 1 row
• ff_pair.h: 1 row
• float_adm_gpu_common.h: none (size_t index helpers)
• float_moment_sum.h: 5 rows
• float_moment_sum_gpu.h: 1 row
• float_motion_sad.h: 1 row
• float_psnr_rows.h: 1 row
• float_vif_gpu_common.h: none (size_t index helpers, fvif_term_index)
• integer_adm.h: 2 rows
• integer_adm_kernels.h: 25 rows
• integer_motion.h: 2 rows
• integer_ssim.h: none (six-int64 layout only)
• integer_vif.h: 1 row
• integer_vif_sv_sq.h: 1 row
• luminance_tools.h: none
• mkdirp.h: none
• moment.h: none
• moment_options.h: none
• motion.h: none
• motion_blend_tools.h: none
• motion_options.h: none
• motion_tools.h: none
• motion_window.h: none
• ms_ssim.h: none
• ms_ssim_decimate.h: none
• niqe_math.h: none
• niqe_model.h: none (double model constants; grep-checked)
• nonfinite_score.h: none (scale * 2u array index ≤ 7)
• offset.h: none
• ordered_sum.h: 1 row
• perceptual_weight.h: none
• picture_copy.h: none
• psnr.h: none
• psnr_hvs_score.h: none
• psnr_options.h: none
• psnr_score.h: 1 row
• psnr_tools.h: none
• pu21_math.h: none
• pu21_ssim.h: none
• simd_dx.h: none (documentation macros)
• speed_cov.h: none
• speed_givens.h: none
• speed_gpu_common.h: none (uint32 geometry fields, no products)
• speed_internal.h: none (uint64_t solve counters, one per solve)
• speed_matmul.h: none
• ssim.h: none
• ssimulacra2_eotf_lut.h: 1 row
• ssimulacra2_math.h: 1 row
• ssimulacra2_pixel_format.h: 1 row
• ssimulacra2_score.h: 1 row
• ssimulacra2_simd_common.h: 1 row
• transnet_v2_score.h: none
• vif.h: none
• vif_log2_table.h: 1 row
• vif_options.h: none
• vif_tools.h: none
• feature_collector.cpp: 1 row
• feature_extractor.cpp: none (registry loops, malloc(sizeof))
• feature_name.cpp: none (string sizes; double bit compare)
• luminance_tools.cpp: none (double EOTFs)
• mkdirp.cpp: none
• picture_copy.cpp: 1 row
• psnr_tools.cpp: none (lookup table)
• iqa/convolve.c: 2 rows
• iqa/convolve.h: none
• iqa/decimate.c: 2 rows
• iqa/decimate.h: none
• iqa/decimate_dim.h: none
• iqa/iqa.h: none
• iqa/iqa_options.h: none
• iqa/iqa_os.h: none
• iqa/math_utils.c: 2 rows
• iqa/math_utils.h: none
• iqa/ssim_accumulate_lane.h: none
• iqa/ssim_simd.h: none
• iqa/ssim_tools.c: 2 rows
• iqa/ssim_tools.h: none
• common/alignment.c: none (vmaf_floorn / vmaf_ceiln on small ints)
• common/alignment.h: none
• common/blur_array.c: none (size_t buffer size; no caller outside the file)
• common/blur_array.h: none
• common/convolution.c: 1 row
• common/convolution.h: none
• common/convolution_avx.c: none (float; (ptrdiff_t)i * stride rows)
• common/convolution_avx512.c: none (float; (ptrdiff_t)i * stride rows)
• common/convolution_internal.h: 1 row
• common/fmaf_exact.h: none
• common/macros.h: none
• third_party/xiph/psnr_hvs.c: 5 rows

CPU scalar, core/src/ runtime¶

• core/src/picture.c: 3 rows
• core/src/picture_pool.cpp: 1 row
• core/src/gpu_picture_pool.cpp: 1 row
• core/src/mem.cpp: 1 row
• core/src/libvmaf.c: 3 rows (read-path sizes only)

x86 SIMD, core/src/feature/x86/¶

• x86/adm_avx2.c: 17 rows
• x86/adm_avx2.h: none (prototypes and comments)
• x86/adm_avx512.c: 14 rows
• x86/adm_avx512.h: none (prototypes and comments)
• x86/cambi_avx2.c: 4 rows
• x86/cambi_avx2.h: none (prototypes and comments)
• x86/cambi_avx512.c: 4 rows
• x86/cambi_avx512.h: none (prototypes and comments)
• x86/ciede_avx2.c: 1 row
• x86/ciede_avx2.h: none (prototypes and comments)
• x86/ciede_avx512.c: 1 row
• x86/ciede_avx512.h: none (prototypes and comments)
• x86/convolve_avx2.c: 1 row
• x86/convolve_avx2.h: none (prototypes and comments)
• x86/convolve_avx512.c: 1 row
• x86/convolve_avx512.h: none (prototypes and comments)
• x86/float_adm_avx2.c: 1 row
• x86/float_adm_avx2.h: none (prototypes and comments)
• x86/float_adm_avx512.c: 1 row
• x86/float_adm_avx512.h: none (prototypes and comments)
• x86/float_motion_avx2.c: 1 row
• x86/float_motion_avx2.h: none (prototypes and comments)
• x86/float_motion_avx512.c: 1 row
• x86/float_motion_avx512.h: none (prototypes and comments)
• x86/float_psnr_avx2.c: 1 row
• x86/float_psnr_avx2.h: none (prototypes and comments)
• x86/float_psnr_avx512.c: 1 row
• x86/float_psnr_avx512.h: none (prototypes and comments)
• x86/integer_ssim_avx2.c: 3 rows
• x86/integer_ssim_avx2.h: none (prototypes and comments)
• x86/moment_avx2.c: 1 row
• x86/moment_avx2.h: none (prototypes and comments)
• x86/moment_avx512.c: 1 row
• x86/moment_avx512.h: none (prototypes and comments)
• x86/motion_avx2.c: 5 rows
• x86/motion_avx2.h: none (prototypes and comments)
• x86/motion_avx512.c: 10 rows
• x86/motion_avx512.h: none (prototypes and comments)
• x86/ms_ssim_decimate_avx2.c: 1 row
• x86/ms_ssim_decimate_avx2.h: none (prototypes and comments)
• x86/ms_ssim_decimate_avx512.c: 1 row
• x86/ms_ssim_decimate_avx512.h: none (prototypes and comments)
• x86/psnr_avx2.c: 4 rows
• x86/psnr_avx2.h: none (prototypes and comments)
• x86/psnr_avx512.c: 2 rows
• x86/psnr_avx512.h: none (prototypes and comments)
• x86/psnr_hvs_avx2.c: 3 rows
• x86/psnr_hvs_avx2.h: none (prototypes and comments)
• x86/speed_avx2.c: 1 row
• x86/speed_avx2.h: none (prototypes and comments)
• x86/speed_avx512.c: 1 row
• x86/speed_avx512.h: none (prototypes and comments)
• x86/speed_matmul_avx2.c: 1 row
• x86/speed_matmul_avx2.h: none (prototypes and comments)
• x86/speed_matmul_avx512.c: 1 row
• x86/speed_matmul_avx512.h: none (prototypes and comments)
• x86/ssim_avx2.c: 1 row
• x86/ssim_avx2.h: none (prototypes and comments)
• x86/ssim_avx512.c: 1 row
• x86/ssim_avx512.h: none (prototypes and comments)
• x86/ssimulacra2_avx2.c: 2 rows
• x86/ssimulacra2_avx2.h: none (prototypes and comments)
• x86/ssimulacra2_avx512.c: 1 row
• x86/ssimulacra2_avx512.h: none (prototypes and comments)
• x86/ssimulacra2_host_avx2.c: 1 row
• x86/ssimulacra2_host_avx2.h: none (prototypes and comments)
• x86/vif_avx2.c: 10 rows
• x86/vif_avx2.h: none (prototypes and comments)
• x86/vif_avx512.c: 9 rows
• x86/vif_avx512.h: none (prototypes and comments)
• x86/vif_statistic_avx2.c: 1 row
• x86/vif_statistic_avx2.h: none (prototypes and comments)

arm64 SIMD, core/src/feature/arm64/¶

• arm64/adm_neon.c: 5 rows
• arm64/adm_neon.h: none (prototypes and comments)
• arm64/cambi_neon.c: 3 rows
• arm64/cambi_neon.h: none (prototypes and comments)
• arm64/ciede_neon.c: 1 row
• arm64/ciede_neon.h: none (prototypes and comments)
• arm64/convolve_neon.c: 1 row
• arm64/convolve_neon.h: none (prototypes and comments)
• arm64/float_adm_dwt2_neon.c: 1 row
• arm64/float_adm_neon.c: 1 row
• arm64/float_adm_neon.h: none (prototypes and comments)
• arm64/float_motion_neon.c: 1 row
• arm64/float_motion_neon.h: none (prototypes and comments)
• arm64/float_psnr_neon.c: 1 row
• arm64/float_psnr_neon.h: none (prototypes and comments)
• arm64/moment_neon.c: 1 row
• arm64/moment_neon.h: none (prototypes and comments)
• arm64/moment_sve2.c: 1 row
• arm64/moment_sve2.h: none (prototypes and comments)
• arm64/motion_neon.c: 2 rows
• arm64/motion_neon.h: none (prototypes and comments)
• arm64/motion_v2_neon.c: 4 rows
• arm64/motion_v2_neon.h: none (prototypes and comments)
• arm64/ms_ssim_decimate_neon.c: 1 row
• arm64/ms_ssim_decimate_neon.h: none (prototypes and comments)
• arm64/psnr_hvs_neon.c: 3 rows
• arm64/psnr_hvs_neon.h: none (prototypes and comments)
• arm64/psnr_neon.c: 2 rows
• arm64/psnr_neon.h: none (prototypes and comments)
• arm64/speed_neon.c: 1 row
• arm64/speed_neon.h: none (prototypes and comments)
• arm64/ssim_neon.c: 1 row
• arm64/ssim_neon.h: none (prototypes and comments)
• arm64/ssimulacra2_arm64_common.h: 1 row
• arm64/ssimulacra2_host_neon.c: 1 row
• arm64/ssimulacra2_host_neon.h: none (prototypes and comments)
• arm64/ssimulacra2_neon.c: 1 row
• arm64/ssimulacra2_neon.h: none (prototypes and comments)
• arm64/ssimulacra2_sve2.c: 1 row
• arm64/ssimulacra2_sve2.h: none (prototypes and comments)
• arm64/vif_neon.c: 5 rows
• arm64/vif_neon.h: none (prototypes and comments)