ADRs tagged testing¶
Auto-generated by scripts/docs/generate-adr-by-tag.sh. Edit ADR Tags: lines to update.
162 ADR(s) carry this tag.
| ID | Title |
|---|---|
| ADR-0001 | Treat uncommitted benchmark result JSON as noise |
| ADR-0006 | Set CLI precision default to %.17g with --precision flag |
| ADR-0015 | CI matrix Linux/macOS/Windows with sanitizers |
| ADR-0024 | Preserve Netflix source-of-truth tests verbatim |
| ADR-0032 | Relocate root unittest script to scripts/ |
| ADR-0110 | Coverage gate -fprofile-update=atomic for parallel meson tests |
| ADR-0111 | Coverage gate lcov → gcovr with ORT in the coverage job |
| ADR-0112 | Testability surface for ort_backend.c static helpers |
| ADR-0119 | Revert CLI precision default to %.6f to honour Netflix golden gate |
| ADR-0125 | MS-SSIM decimate SIMD fast paths (AVX2 + AVX-512) |
| ADR-0132 | Port Netflix#1406 — feature_collector mount/unmount model-list bugfix |
| ADR-0347 | Sanitizer matrix — concrete test-set scope per sanitizer |
| ADR-0368 | External-competitor benchmark harness — wrapper-only architecture |
| ADR-0398 | MyTestCase upstream migration — partial port (golden-pinned files deferred) |
| ADR-0404 | Keep nightly.yml + fuzz.yml red until underlying bugs land |
| ADR-0438 | CLI parser short-option handler coverage invariant |
| ADR-0481 | ADM p-norm Parameter Hardcoded at 3.0 — Deferral Decision |
| ADR-0493 | Test YUV fixtures must be md5-verified, not just present-by-name |
| ADR-0494 | Restore the non-golden Python test suite to green |
| ADR-0495 | MCP server probe-driven bug-fix cluster (2026-05-17) |
| ADR-0645 | Thread integer ADM p-norm through SIMD callbacks |
| ADR-0656 | External-bench wrappers emit registry competitor keys |
| ADR-0694 | Tighten clang-tidy enforcement + confirm sanitizers as required CI gates |
| ADR-0783 | Kubernetes end-to-end integration test harness — kind + kuttl |
| ADR-0806 | VmafFeatureDictionary caller-ownership contract |
| ADR-0884 | SYCL kernel coverage round 2 — five additional CPU-vs-SYCL parity gates |
| ADR-0886 | CUDA kernel parity test coverage — round 2 gap-fill |
| ADR-0907 | Wall-clock perf regression gate over the multi-resolution baseline |
| ADR-0908 | Slow-test audit (2026-05-30) — no >30 s tests found; install slow marker as a future gate |
| ADR-0947 | CUDA kernel parity coverage — round 3 (float-path twins + ssimulacra2) |
| ADR-0956 | CUDA kernel parity coverage — round 4 (last 5 uncovered kernels) |
| ADR-0959 | Metal kernel parity coverage round 4 — closeout |
| ADR-0970 | test_gpu_picture_pool.c: remove unused malloc + dead code (Round 27 audit D.3 + D.4) |
| ADR-0971 | Test suite: NULL-check malloc in 3 test files (Round 27 audit D.1) |
| ADR-0991 | Second-Opinion Batch Materializer — Smoke-Run Scaffold and Test Fix |
| ADR-1090 | Fix CUDA stream and event leaks on init error paths |
| ADR-1093 | Disable two recurring-failure tests via should_fail while root cause is under investigation |
| ADR-1195 | Record and verify which source revision the dev container was built from |
| ADR-1196 | Dispatch the SpEED dense matrix product through bit-exact AVX2 / AVX-512 kernels |
| ADR-1197 | The threaded flush leaves GPU extractors to their own backend flush |
| ADR-1198 | An unknown changelog.d/ subdirectory fails the run instead of warning |
| ADR-1199 | Order caller-written CUDA pictures once per frame, at the dispatch point |
| ADR-1204 | GPU ADM contrast-masking twins clamp the far edge instead of mirroring it |
| ADR-1206 | Every CUDA parity test also runs against a second, larger fixture |
| ADR-1207 | A test gates every feature's score against the host instruction set |
| ADR-1209 | --gpumask keeps rejecting negative values; the test script uses a positive mask |
| ADR-1216 | The GPU motion3 twins apply motion_fps_weight exactly once |
| ADR-1217 | The GPU float-VIF kernels read vif_sigma_nsq and vif_enhn_gain_limit from their options |
| ADR-1218 | The GPU SpEED twins zero the device solution and report singularity from the temporal path |
| ADR-1219 | The HIP and Metal CAMBI twins use the shared TVI bisection and the CPU's border rules |
| ADR-1220 | The GPU float-ADM kernels honour adm_p_norm, adm_bypass_cm and adm_skip_scale0 |
| ADR-1221 | clip_db is a ceiling on the MS-SSIM dB output, not a clamp on the linear score |
| ADR-1257 | Retire the Darwin three-tap integer-ADM DWT2 compatibility dispatch |
| ADR-1264 | The HIP scaffold posture reports -ENOSYS, and its tests check both sites |
| ADR-1274 | Make HISS-21 claims replayable and platform-gated |
| ADR-1278 | Use spawn-safe Python process execution and the canonical five-parameter logistic curve |
| ADR-1292 | Resolve the vmaf compatibility shim by file location instead of re-import |
| ADR-1295 | Correct sureal's Gaussian density for unanimously rated stimuli in-process |
| ADR-1296 | GPU init failure paths are tested device-free, by compiling the backend TU against runtime stubs |
| ADR-1310 | Reuse the merge-base mypy gate in required CI |
| ADR-1312 | GPU option aliases match CPU collector keys |
| ADR-1316 | Mark extractor options whose implementation is default-only |
| ADR-1321 | Pre-RC1 CI flake remediation and contract alignment |
| ADR-1324 | Resolve GPU float-SSIM auto-scale before backend initialization |
| ADR-1326 | Use a fixed-point oracle for SYCL motion-add-UV parity |
| ADR-1334 | Extend MS-SSIM option parity to the Metal twin |
| ADR-1335 | Bind research-digest debt to the trusted merge base |
| ADR-1336 | Tear down CUDA resources in their owning context |
| ADR-1342 | RC1 external tester evidence bundle |
| ADR-1361 | Scale the psnr_hvs cross-backend tolerance with the CPU's float-sum length |
| ADR-1386 | One script runs the home GPU box's RC3 verify commands, row by row, under per-device locks |
| ADR-1395 | SYCL kernels use no scratch memory on Intel GPUs |
| ADR-1397 | GPU psnr_hvs twins reproduce the CPU's running float sum bit for bit |
| ADR-1401 | psnr_hvs_sycl and psnr_hvs_hip return the CPU's scores bit for bit; the fp64-free masking threshold is an integer square root |
| ADR-1409 | float_motion_cuda adds its SAD in the CPU's order and returns the CPU's scores bit for bit |
| ADR-1411 | float_motion_sycl adds its SAD in the CPU's order and returns the CPU's scores bit for bit |
| ADR-1412 | float_vif_cuda computes the CPU's arithmetic, adds in the CPU's order and returns its scores bit for bit |
| ADR-1414 | float_ms_ssim_sycl computes the CPU's arithmetic and returns its per-scale means bit for bit |
| ADR-1415 | every x86 SIMD library is built without FP contraction |
| ADR-1416 | adm_cuda takes its CSF weights, its rounding shifts and its score conclusion from the CPU's routines and folds the denominator once per row |
| ADR-1419 | float_motion_hip stores its differences transposed and adds each row in the CPU's order |
| ADR-1420 | float_adm_cuda computes the CPU's arithmetic, divides through the host's reciprocal estimate and returns the CPU's scores bit for bit |
| ADR-1422 | float_vif_sycl computes the CPU's arithmetic without an fp64 type and returns its scores bit for bit |
| ADR-1423 | adm_hip takes its weights, shifts and score conclusion from the CPU, folds the denominator once per row and clears its accumulators after the upload |
| ADR-1424 | integer_ssim_cuda adds its terms in the CPU's raster order, on the host, and returns the CPU's score bit for bit |
| ADR-1426 | ciede_cuda computes the CPU's arithmetic and adds in the CPU's order; what remains is the math library, and the gate bounds it |
| ADR-1427 | A HIP frame queues its accumulator clears after its upload |
| ADR-1428 | Exact GPU twins are declared by one fragment file each, not by a shared literal |
| ADR-1430 | speed_chroma_cuda keeps its correctly rounded log2; the gate bounds what glibc's log2f adds |
| ADR-1432 | vif_sycl computes the gain terms of the integer VIF in exact integer arithmetic and returns the CPU's scores bit for bit |
| ADR-1433 | ssimulacra2_cuda returns the sums of the CPU's loops, formed on the device from integer increments per binade |
| ADR-1434 | float_adm_sycl computes the CPU's arithmetic without an fp64 type, adds in the CPU's order and returns the CPU's scores bit for bit |
| ADR-1435 | vif_hip reads the CPU's log2 table instead of evaluating log2f() on the device, and returns the CPU's scores bit for bit |
| ADR-1436 | ciede_sycl runs the CPU's statements on fp32 pairs and adds in the CPU's order; it lands where the CUDA twin does, 1.4e-11 from the CPU |
| ADR-1437 | motion_hip, motion_v2_hip, psnr_hip, integer_ms_ssim_hip and cambi_hip are declared exact twins; float_psnr_hip and float_moment_hip are not |
| ADR-1438 | integer_ssim_hip adds its terms in the CPU's raster order at every frame size and returns the CPU's score bit for bit |
| ADR-1440 | float_psnr_hip adds its squared differences as integers and returns the CPU's score bit for bit |
| ADR-1441 | float_ssim_hip forms its window sums through the arithmetic float_ms_ssim_hip shares with the CPU and returns the CPU's score bit for bit |
| ADR-1442 | float ADM divides; the processor's reciprocal estimate leaves the reference and the CUDA twin |
| ADR-1443 | integer_ssim_sycl computes the CPU's fp64 term in 64-bit integers and adds in the CPU's order; it returns the CPU's ssim bit for bit |
| ADR-1444 | float_vif_hip runs the arithmetic of the CUDA twin from one shared header and returns the CPU's scores bit for bit |
| ADR-1445 | ssimulacra2_hip evaluates the CPU's fp64 terms and returns the sums of the CPU's loops |
| ADR-1446 | ssimulacra2_sycl forms the CPU's fp64 terms in 64-bit integers and returns the sums of the CPU's loops; it returns the CPU's score bit for bit |
| ADR-1447 | float_moment_hip adds the float squares the CPU adds, and is bit-identical while the CPU's own sum is exact |
| ADR-1448 | ciede_hip runs the CPU's arithmetic in fp32 pairs, from the header the SYCL twin runs; what remains is glibc's powf and the last bits of a pair |
| ADR-1449 | float_moment_sycl adds the float squares the CPU adds, and is bit-identical while the CPU's own sum is exact |
| ADR-1450 | float_psnr_sycl adds its squared differences as integers, and is bit-identical to the CPU |
| ADR-1451 | adm_sycl, motion_sycl, motion_v2_sycl, psnr_sycl, float_ssim_sycl and cambi_sycl are declared exact twins; speed_chroma_sycl is not |
| ADR-1452 | the gate bounds speed_chroma_hip against the CPU by what glibc's log2f adds, as it does for the CUDA twin |
| ADR-1453 | float_moment_cuda adds the float squares the CPU adds, and is bit-identical while the CPU's own sum is exact |
| ADR-1455 | float_psnr_cuda adds its squared differences as integers, and is bit-identical to the CPU |
| ADR-1456 | vif_cuda keeps its device log2f(), proven equal to the CPU's log2 table on every entry, and is declared an exact twin |
| ADR-1457 | motion_cuda, motion_v2_cuda, psnr_cuda, float_ssim_cuda, float_ms_ssim_cuda and cambi_cuda are declared exact twins |
| ADR-1458 | float_adm_hip runs the CPU's arithmetic from the header the CUDA twin runs and returns the CPU's scores bit for bit |
| ADR-1459 | SpEED's covariance kernels return the scalar kernel's bits; they vectorise across sums, not within one |
| ADR-1460 | speed_temporal becomes a parity-gate feature with a derived bound, and every registered twin of a gated backend has to be a gate cell |
| ADR-1461 | no C or C++ translation unit is built with floating-point contraction; the strict policy is a project argument |
| ADR-1462 | vif_cuda reads the CPU's log2 table instead of evaluating log2f() on the device |
| ADR-1463 | float_ssim_sycl forms the CPU's fp64 terms in 64-bit integers and adds them on the host in the CPU's raster order |
| ADR-1464 | float_ssim_cuda adds its frame sums in the CPU's raster order, on the host |
| ADR-1465 | float_ms_ssim_cuda adds the terms of every scale in the CPU's raster order, on the host |
| ADR-1466 | float_ms_ssim_sycl stores every window's l, c and s of every scale and adds them on the host in the CPU's raster order |
| ADR-1467 | ciede.c writes its squares as products, so ciede2000 no longer depends on the compiler or on the C library's powf for them; a GCC build moves by up to 2e-11 |
| ADR-1468 | A SYCL kernel requires only a sub-group size every default AOT target accepts (16 or 32); the six kernels that required 8 move to 16 |
| ADR-1470 | An enum that C and C++ translation units both see has one size: no C++-only underlying type other than int's width |
| ADR-1475 | The quantisation step of integer ADM is Netflix's expression again, so vmaf_v0.6.1 returns Netflix master's bits |
| ADR-1476 | ciede2000() forms its two products in float, as Netflix's source does; the double casts of PR #552 are removed and the three GPU twins follow |
| ADR-1477 | SpEED evaluates Netflix's fp64 expressions again, and its GPU twins form the entropies and the score on the host with the same statements, so every twin returns the CPU's scores bit for bit on any C library |
| ADR-1487 | code inherited from Netflix/vmaf evaluates as Netflix's source does, a difference needs an ADR, and a guard compares every emitted value against the recorded upstream head |
| ADR-1488 | the psnr_hvs masking threshold is the double root of a float product, as Netflix's source writes it; the double product of PR #552 is removed and the AVX2, NEON, CUDA, HIP and SYCL forms follow, bit for bit |
| ADR-1489 | The CSF weights of float ADM are Netflix's float arithmetic again, so float_adm differs from Netflix by the division alone |
| ADR-1492 | Tester image with one report command, hardware reports as tracked files |
| ADR-1493 | macOS tester bundle, an exception to container-only publishing |
| ADR-1495 | icx and icpx builds link glibc's libm, not Intel's libimf |
| ADR-1496 | The macOS tester bundle runs the parity gate's Metal cells and reports per state row what it measured |
| ADR-1497 | The float_moment twins form the CPU's rounded second-moment sum past 2^53 units, and return the CPU's bits on every frame |
| ADR-1499 | The float_psnr twins add each row's exact sum in the CPU's order, and return the CPU's bits on every frame |
| ADR-1500 | The NEON and SVE2 float_moment kernels add in the scalar's order and return its bits on every input and vector length |
| ADR-1501 | The float_adm_sycl term kernel takes the large register file and leaves the sub-group size to the compiler, so it uses no scratch memory on Xe2 |
| ADR-1502 | Tests that assert an exact result compare floats by their bits through one helper, core/test/float_bits.h, which treats a NaN as identical to nothing |
| ADR-1503 | Every published tester artifact carries its licence texts, an attested SPDX SBOM and the source its copyleft parts require, and a gate refuses a file with no recorded licence |
| ADR-1505 | An Intel GPU tester image with a backend-neutral GPU section in the report |
| ADR-1509 | An NVIDIA GPU tester image that ships no NVIDIA file and measures every CUDA twin on a tester's GPU |
| ADR-1511 | An AMD GPU tester image that ships only the ROCm runtime files the HIP build loads, with the source of its LGPL parts |
| ADR-1515 | A native Windows tester zip for x64 and Arm64, built by the hosted runners with MSVC and a static C runtime |
| ADR-1516 | A Windows CUDA tester zip that ships no NVIDIA file and measures every CUDA twin on a tester's Windows PC |
| ADR-1528 | Every test file belongs to a suite that a required check runs |
| ADR-1566 | A Windows SYCL tester zip built with /MD that carries its runtime beside every program and measures every SYCL twin on a tester's Intel GPU |
| ADR-1568 | A test runs once in CI |
| ADR-1591 | Publish every archive and image at the strongest compression its documented consumers open |
| ADR-1594 | zstd image layers with a Docker Engine 23.0 floor, and zopfli for the Windows zips |
| ADR-1595 | Build and run what the push-only and release-only workflows publish, before they publish |
| ADR-1687 | Require the pull-request release legs through the aggregator |
| ADR-1700 | The tester selectors follow their own paths, not the full-mode fallback |
| ADR-1701 | Build and test the tester image every night on master |
| ADR-1707 | Cut v1.0.0-rc.3 without waiting for outside-hardware reports |
| ADR-1713 | Rust feature-extractor twins behind the unchanged C ABI (RC4 framework) |
| ADR-1806 | Run Metal kernel files on the host through a Metal Shading Language shim in tests |
| ADR-1830 | vif_sycl runs at SIMD-16 only; the SIMD-32 kernels and VMAF_SYCL_VIF_SUBGROUP_SIZE are removed |
| ADR-1930 | sycl_device_asan puts the device sanitizer on every SYCL compile and the link |
| ADR-2198 | A tester leg builds where its inputs change, and no release is cut on a leg nobody saw green |
| ADR-2343 | Reference-exact extractors by default, with a named Netflix compatibility mode |