ADRs tagged ssimulacra2¶
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20 ADR(s) carry this tag.
| ID | Title |
|---|---|
| ADR-0130 | SSIMULACRA 2 scalar implementation |
| ADR-0161 | SSIMULACRA 2 SIMD bit-exact ports — AVX2 + AVX-512 + NEON (T3-1 + T3-2) |
| ADR-0162 | SSIMULACRA 2 IIR blur SIMD ports — AVX2 + AVX-512 + NEON (T3-1 phase 2) |
| ADR-0163 | SSIMULACRA 2 picture_to_linear_rgb SIMD ports (T3-1 phase 3) |
| ADR-0164 | SSIMULACRA 2 snapshot-JSON regression gate (T3-3) |
| ADR-0201 | ssimulacra2 Vulkan kernel |
| ADR-0206 | ssimulacra2 CUDA + SYCL twins |
| ADR-0213 | SSIMULACRA 2 SVE2 SIMD parity |
| ADR-0252 | ssimulacra2 Vulkan host-path AVX2 + NEON SIMD (T-GPU-OPT-VK-2) |
| ADR-0410 | ssimulacra2_cuda GPU module leak + per-scale malloc removal |
| ADR-0456 | SSIMULACRA2 CUDA Blur: 3-Channel Kernel Fusion and V-Pass Transpose for Coalesced Access |
| ADR-0467 | SSIMULACRA2 AVX-512 + NEON IIR Blur / picture_to_linear_rgb ULP Audit — Clean Close |
| ADR-0594 | Per-kernel hip_cu_extra_flags dispatch — disable FMA contraction for ssimulacra2_blur HIP HSACO |
| ADR-0973 | Master CI fixes — Metal MS-SSIM fixture dim + ssimulacra2 icpx XYB bit-exactness |
| ADR-1363 | The SYCL ssimulacra2 twin is device-resident, and float_ms_ssim_sycl waits once per frame |
| ADR-1390 | The HIP ssimulacra2 twin is device-resident with tiled row-pass Gaussian blur |
| ADR-1391 | The CUDA ssimulacra2 twin is device-resident |
| ADR-1433 | ssimulacra2_cuda returns the sums of the CPU's loops, formed on the device from integer increments per binade |
| ADR-1445 | ssimulacra2_hip evaluates the CPU's fp64 terms and returns the sums of the CPU's loops |
| ADR-1446 | ssimulacra2_sycl forms the CPU's fp64 terms in 64-bit integers and returns the sums of the CPU's loops; it returns the CPU's score bit for bit |