ADRs tagged ssim¶
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18 ADR(s) carry this tag.
| ID | Title |
|---|---|
| ADR-0458 | SYCL CAMBI queue-sync collapse + SSIM horizontal SLM staging |
| ADR-0564 | Real integer_ssim GPU kernels (CUDA, HIP, SYCL) — replace silent float_ssim substitution |
| ADR-0589 | Metal float_ssim option parity — enable_lcs, enable_db, clip_db, scale |
| ADR-0754 | 0754-cuda-ssim-vert-combine-ldg-pinned-leak.md |
| ADR-0784 | AVX2 SIMD path for integer SSIM horizontal moment accumulation |
| ADR-0871 | SSIM SIMD dispatch installation must be pthread_once-guarded |
| ADR-1033 | CPU-side scoring NaN/UB guards across PSNR/SSIM/MS-SSIM/ADM/CAMBI/MOTION |
| ADR-1370 | float_ssim_sycl decimates on the device, bit-identical to the CPU |
| ADR-1399 | float_ssim_cuda decimates and convolves on the device with the CPU's arithmetic |
| ADR-1405 | float_ssim_hip decimates on the device, bit-identical to the CPU |
| ADR-1424 | integer_ssim_cuda adds its terms in the CPU's raster order, on the host, and returns the CPU's score bit for bit |
| ADR-1438 | integer_ssim_hip adds its terms in the CPU's raster order at every frame size and returns the CPU's score bit for bit |
| ADR-1441 | float_ssim_hip forms its window sums through the arithmetic float_ms_ssim_hip shares with the CPU and returns the CPU's score bit for bit |
| ADR-1443 | integer_ssim_sycl computes the CPU's fp64 term in 64-bit integers and adds in the CPU's order; it returns the CPU's ssim bit for bit |
| ADR-1463 | float_ssim_sycl forms the CPU's fp64 terms in 64-bit integers and adds them on the host in the CPU's raster order |
| ADR-1464 | float_ssim_cuda adds its frame sums in the CPU's raster order, on the host |
| ADR-1465 | float_ms_ssim_cuda adds the terms of every scale in the CPU's raster order, on the host |
| ADR-1466 | float_ms_ssim_sycl stores every window's l, c and s of every scale and adds them on the host in the CPU's raster order |